FIG. 5 is a diagram showing a circuit construction of a prior art level shift circuit. In FIG. 5, reference numeral 500 designates a level shift circuit. A drain of a source follower enhancement type FET 1(Q1) is connected to a positive power supply 30, and a gate thereof is connected to an input terminal 10 to which an output signal of the prior stage circuit is input, and a source thereof is connected to the anode of the level shift diode 2. A constant current source 3 is connected between the cathode of the level shift diode 2 and the negative power supply 40 and an output terminal 20 is taken from the connection node of the cathode of the level shift diode 2 and the constant current source 3, thus constituting a level shift circuit.
Here, while in the above example the level shift diode 2 comprises two diodes D1 and D2 connected in series to each other, the number of diodes is not restricted thereto and can be determined in accordance with the voltage to be dropped. In addition, the constant current source 3 is constituted by a depletion FET having its gate and its source connected with each other.
A description is given of an operation hereinafter.
When it is supposed that a current which is made to flow through the level shift circuit 500 by the constant current source 3 is I.sub.const and that the source follower enhancement type FET 1 is operated in the saturation region, the level shift amount V.sub.gs between its gate and its source, is represented by the following formula (1). ##EQU1## here, K: gain coefficient of the enhancement type FET 1(Q1) V.sub.th : threshold voltage of the enhancement type FET 1(Q1)
From equation (1), by setting the current I.sub.const flowing through the constant current source 3 to an appropriate value, the level shift amount V.sub.gs at the source follower enhancement type FET 1(Q1) is determined. The reason why the enhancement type FET 1(Q1) is employed for the source follower FET is because the enhancement type FET can produce a desired level shift with less current I.sub.const than a depletion type FET, thereby resulting in a low power dissipation. Here, when the voltage difference between the gate and the source in the source follower enhancement type FET 1(Q1) is larger than its junction voltage .phi..sub.B (about 0.7 V), a forward direction current flows between the gate and source of the FET, and the level shift amount V.sub.gs falls within 0 to 0.7 V and does not exceed that range.
In this level shift circuit, in order to increase the level shift of the entire circuit V.sub.shift to a value larger than the junction voltage .phi..sub.B (about 0.7 V), the level shift diode 2 is employed. The level shift amount at one level shift diode D1, D2 is approximately equal to its junction voltage difference .phi..sub.B (about 0.7 V) and the level shift amount of the entire circuit V.sub.shift is represented by the following formula (2) providing an appropriate number of level shift diodes enables setting of a level shift amount at any arbitrary value larger than 0.7 V. ##EQU2##
In the prior art level shift circuit constituted as described above, if the device parameters of the source follower enhancement type FET 1(Q1) such as threshold voltages and gain coefficients deviate from predetermined set values, the variations in the device parameters vary the level shift amount V.sub.gs a function of the current I.sub.const of the source follower enhancement type FET 1(Q1), thereby resulting in variations in the output voltage of the entire circuit of the level shift circuit, that is, the amount of the level shift.
Here, variations in the threshold value of enhancement type FETs are about several tens of mV for FETs made on the same wafer, and reach about 100 mV for FETs made on different wafers.